I want to talk about first simulating an RTL design that contains of soft CPU, and debugging the firmware that ran on that soft CPU after the simulation has completed.
(From: https://tomverbeure.github.io/2022/02/20/GDBWave-Post-Simulation-RISCV-SW-Debugging.html)
Novel idea of using GDB to debug software running on a soft-core processor in an FPGA simulation, AFTER the simulation is completed!